1. Field of the Invention
The present invention relates to a method for the fabrication of MOS devices of the type in which elements are isolated from each other by field oxide films and channel stoppers.
2. Description of the Related Art
In monolithic ICs, it is necessary to electrically isolate a large number of elements from each other that are arranged on a single semiconductor chip. One of the typical electrical isolation techniques is the dielectric isolation technique, the most typical of which is the LOCOS method, which electrically isolates circuit elements by field oxide films.
Furthermore, a channel stopper that is a highdensity impurity doped diffusion layer having the same conductivity as a semiconductor substrate is formed below a field oxide film so that the threshold voltage of a parasitic MOS transistor, whose channel region exists below the field oxide film, becomes higher than the potential of an interconnection over the field oxide film to cut off the parasitic MOS transistor within the IC driving voltage completely, and thereby ensure electrical isolation among the circuit elements.
FIG. 2 illustrates the steps of a prior art method for the fabrication of a semiconductor device in which electric isolation among the circuit elements is effected by field oxide films and channel stoppers and MOS transistors are created in the element regions surrounded by the field oxide films.
According to this prior art method, as shown in FIG. 2(a), first a SiO.sub.2 film 12 for padding is formed over the surface of a p-type Si wafer 11 and then a Si.sub.3 N.sub.4 film 13, approximately 1000 to 3000 .ANG. in thickness, is deposited on the SiO.sub.2 film 12 and is patterned to define the region of elements to be fabricated.
Next, as shown in FIG. 2(b), a p-type impurity or dopant, such as BF.sub.2 14, is diffused at a rate of about 1.times.10.sup.13 -1.times.10.sup.14 cm .sup.-2 into the Si wafer 11 by using the Si.sub.3 N.sub.4 film 13 as a mask by ion implantation.
Thereafter, the semiconductor structure thus obtained is subjected to thermal oxidation so that the Si.sub.3 N.sub.4 film 13 becomes an antioxidant film as shown in FIG. 2(c) and the regions of the Si substrate 11 unmasked by the Si.sub.3 N.sub.4 film 13 are selectively oxidized to form SiO.sub.2 films 15 that are field oxide films.
Meanwhile, the ion-implanted impurities 14 in the Si wafer are diffused by heat dissipated in the thermal oxidation process so that p.sup.+ -type diffusion layers 16 are formed below the SiO.sub.2 films 15 in selfalignment therewith and simultaneous with the formation thereof.
Next, as shown in FIG. 2(d), Si.sub.3 N.sub.4 film 13 and SiO.sub.2 films 12 are removed so that a SiO.sub.2 film 17 that becomes a gate oxide film is formed over the element region surrounded by the SiO.sub.2 films 15. Thereafter, a polycrystalline Si film 18 is deposited on the SiO.sub.2 films 17 and 15 and is patterned in the form of a gate electrode.
In the succeeding step, high-density ion-implantation of an N-type impurity, such as arsenic, into the Si wafer is carried out by using the polycrystalline Si film 18 and the SiO.sub.2 films 15 as a mask. Next the semiconductor structure thus obtained is subjected to a heat treatment to diffuse the implanted impurities. Then, N.sup.+ -type diffusion layers 19 that become a source and a drain, respectively, are formed in a self-alignment relationship with the polycrystalline Si film 18, whereby a MOS transistor generally indicated by the reference numeral 20 is fabricated.
The actual MOS transistor fabrication process further includes the step of forming an interconnection and the step of forming a passivation film, but these steps shall not be described in this specification because they are not a function of the present invention.
However, in the semiconductor device fabricated by the prior art method described above, the P.sup.+ -type diffusion layer 16 extends to the edge of the SiO.sup.2 film 15 and makes contact with the N.sup.+ -type diffusion layer 19 as best shown in FIG. 2(d). As a result, when the amount of dopant is increased excessively in order to raise the threshold value of a parasitic MOS transistor by utilizing the stopper channels, the dopant density of the P.sup.+ -type diffusion layer 16 is also increased at the junction.
As a consequence, the junction capacitance between the P.sup.+ -type diffusion layer 16 and the P.sup.+ -type diffusion layer 19 is increased so that the speed of the MOS transistor 20 is decreased. In addition, the breakdown voltage of the junction between the P.sup.+ -type diffusion layer 16 and the N.sup.+ -type diffusion layer 19 drops so that reliability of the MOS transistor 20 is adversely affected.
Furthermore, when the P.sup.+ -type diffusion layer 16 extends towards the edge of the N.sup.+ -type diffusion layer 15, the channel contraction effect occurs in the MOS transistor 20 so that the threshold voltage of the transistor 20 becomes higher. This is another reason why the speed of the MOS transistor 20 becomes slow.
In view of the above, the primary object of the present invention is to provide a method for the fabrication of MOS devices which are fast and highly reliable in operation.